? integrated circuits group lh 28 f16 0 b v h e - bt l 9 0 fla sh me mor y 1 6 m ( 2 m 8/1m x 16 ) (model no.: lh f 16 v 11 ) spec no.: el 10 y 079 a issue date: se pt em b er 8 , 19 99 p reliminary p roduct s pecifications
lhf16vll l handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. *when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). l offce electronics l instrumentation and measuring equipment l machine tools *audiovisual equipment *home appliance acommunication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliabilitv, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. kontrol and safety devices for airplanes, trains, automobiles, and other transportation equipment l mainframe computers atraffic control systems agas leak detectors and automatic cutoff devices orescue and security equipment *other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. l aerospace equipment l communications equipment for trunk lines *control equipment for the nuclear power industry @medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. l please direct all queries regarding the products covered herein to a sales representative of the company. rev. 1.1
shari= lhf16vll contents page page 1 introduction.. ........................................................... .3 1.1 features ........................................................................ 3 1.2 product overview.. ...................................................... .3 2 principles of operation.. ..................................... .7 2.1 data protection ............................................................ . 8 3 bus operation ............................................................ 8 3.1 read.. ........................................................................... .8 3.2 output disable .............................................................. 8 3.3 standby.. ...................................................................... .8 3.4 deep power-down ....................................................... 8 3.5 read identifier codes operation.. ............................... .9 3.6 write.. .......................................................................... .9 5 design considerations ...................................... 20 5.1 three-line output control ....................................... 20 5.2 ry/by# and block erase and word/byte write polling ...................................................................... 20 5.3 power supply decoupling ........................................ 20 5.4 v,, trace on printed circuit boards.. ...................... 20 5.5 v,--, v,,, rp# transitions.. ..................................... 21 5.6 power-up/down protection.. .................................... 21 5.7 power dissipation.. ................................................... 21 4 command definitions ............................................. 9 4.1 read array command.. .............................................. 12 4.2 read identifier codes command ............................... 12 4.3 read status register command.. ............................... 12 4.4 clear status register command.. ............................... 12 4.5 block erase command ............................................... 12 4.6 word/byte write command.. ..................................... 13 4.7 block erase suspend command ................................ 13 4.8 word/byte write suspend command.. ...................... 14 4.9 considerations of suspend.. ....................................... 14 4.10 block locking ........ ..!. .............................................. 14 4.10.1 vpp=vil for complete protection.. .................... 14 4.10.2 wp#=v,, for block locking.. ............................ 1-l 4.10.3 wp#=v,, for block unlocking.. ........................ 14 6 electrical specifications ............................... 22 6.1 absolute maximum ratings ..................................... 22 6.2 operating conditions ................................................ 22 6.2.1 capacitance ......................................................... 22 6.2.2 ac input/output test conditions ....................... 23 6.2.3 dc characteristics .............................................. 24 6.2.4 ac characteristics - read-only operations.. ..... 26 6.2.5 ac characteristics - write operations ............... 29 6.2.6 alternative ce#-controlled writes.. ................... 3 1 6.2.7 reset operations ................................................. 33 6.2.8 block erase and word/byte write performance 34 7 package and packing specifications.. ....... 35 rev. 1.02
lhf16vll 2 lh28f 160bvhe-btl90 16m-bit (2mbit x 8 / 1mbit x 16) boot block flash memory n single voltage operation - 2.7v-3.6v vcc and vpp read/write/erase operation h high-block erase and word/byte write performance - usable 12v+o.6v vpp w user-configurable x8 or x 16 operation w high-performance access time - 90ns(v,,=2,7v-3.6v, t,=-40c to +85?c) n optimized array blocking architecture - two 4k-word boot blocks - six 4k-word parameter blocks - thirty-one 32k-word main blocks - bottom boot location w extended cycling capability - 100,000 block erase cycles w low power management - deep power-down mode - automatic power savings mode decreases icc in static mode n enhanced data protection features - absolute protection with vpp=gnd - block erase and word/byte write lockout during power transitions - boot blocks protection with wp#=vil n enhanced automated suspend options - word/byte write suspend to read - block erase suspend to word/byte write - block erase suspend to read n automated word/byte write and block erase - command user interface - status register w sram-compatible write interface n industry-standard packaging - 4%lead tsop n etoxm* nonvolatile flash technology w cmos process (p-type silicon substrate) n not designed or rated as radiation hardened sharp?s LH28F160BVHE-BTL90 flash memory is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. LH28F160BVHE-BTL90 can operate at v,,- -2 7v-3.6v and v,,=2.7v-3.6v. its low voltage operation capability realize battery life and suits for cellular phone application. its boot, parameter and main-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for portable terminals and personal computers. its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the LH28F160BVHE-BTL90 offers two levels of protection: absolute protection with v,, at gnd, selective hardware boot block locking. these alternatives give designers ultimate control of their code security needs. the lh28f160bvhebtl90 is manufactured on sharp?s 0.35nm etoxtm* process technology. it come in industry- standard package: the 48-lead tsop ideal for board constrained applications. *etox is a trademark of intel corporation. rev. 1.1
sharp lhf16vll 3 1 introduction this datasheet contains LH28F160BVHE-BTL90 specifications. section 1 provides a flash memory overview. sections 2,3,4 and 5 describe the memory organization and functionality. section 6 covers electrical specifications. 1.1 features key enhancements of LH28F160BVHE-BTL90 flash memory are: l 2.7v-3.6v v,, and v,, read/write/erase operations *enhanced suspend capabilities l boot block architecture please note following contents: l vpplk has been lowered to 1.5v to support 2.7v-3.6v block erase and word/byte write operations. the vpp voltage transitions to gnd is recommended for designs that switch v,, off during read operation. 1.2 product overview the LH28F160BVHE-BTL90 is a high-performance 16m- bit flash memory organized as 2m-byte of 8 bits or lm- word of 16 bits. the 2m-byte/lm-word of data is arranged in two 8k-byte/4k-word boot blocks, six 8k-byte/4k- word parameter blocks and thirty-one 64k-byte/32k-word main blocks which are individually erasable in-system. the memory map is shown in figure 3. 4 choice of v,, and v,, combinations, as shown in table 1, to meet system performance and power txpectations. v,, at 2.7v-3.6v eliminates the need for a ;eparate 12v converter, while v,,=12v maximizes block :rase and word/byte write performance. in addition to jexible erase and program voltages, the dedicated v,, pin sives complete data protection when v, shari= lhf16vll 4 the boot blocks can be locked for the wp# pin. block erase or word/byte write for boot block must not be carried out by wp# to low and rp# to v,,. the status register indicates when the wsm?s block erase or word/byte write operation is finished. the ry/by# output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status polling using ry/by# minimizes both cpu overhead and system power consumption. when low, ryfby# indicates that the wsm is performing a block erase or word/byte write. ry/by#-high z indicates that the wsm is ready for a new command, block erase is suspended (and word/byte write is inactive), word/byte write is suspended, or the device is in deep power-down mode. the access time is 90ns (tav v) over the operating temperature range (-40c to + 5c) 8 and v,, supply voltage range of 2.7v-3.6v. the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i,,, current is 3ma at 2.7v-3.6v v,,. when ce# and rp# pins are at v,,, the i,, cmos standby mode is enabled. when the rp# pin is at gnd, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (tphqv) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (tphel) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared. the device is available in 48-lead tsop (thin small outline package, 1.2 mm thick). pinout is shown in figure 2. rev. 1.1
sharp lhf16vll r oulput buffer illpul buffer i i figure 1. block diagram i i al5 am a13 ai? aii alo a9 ?48 ai9 nc we# rf% vpp wp# rylby# ?418 a17 a7 a5 2 a3 a? al e 2 3 0 48 47 46 j i i ?416 byte# gnd 6 i 8 9 10 11 13 14 15 16 17 32 ?18 31 19 20 22 23 d 24 4%lead tsop standard pinout 12mm x 20mm top view 45 44 43 42 41 40 39 38 37 36 35 34 33 30 29 28 21 26 25 dqdai dq7 ddi4 dq6 dqn dc% dqiz dqa vcc dqli dq3 dqlo dq2 dqs dqi dqs dqo oe# gnd ce# a0 figure 2. tsop &lead pinout rev. 1.02
sharf= lhj36vll 6 symbol a-1 ao-h9 table 2. pin descriptions type name and function address inputs: addresses are internally latched during a write cycle. a-1 : byte select address. not used in x16 mode. input a,-a,, : : row address. selects 1 of 2048 word lines. all=%4 : column address. selects 1 of 16 bit lines. ats-a,, : main block address. (boot and parameter block addresses are a12-a19.) data input/outputs: dq,-dq,:inputs data and commands during cui write cycles; outputs data during memory array, status register and identifier code read cycles. data pins float to high-impedance when the chip is ?qo-dqrs input/ deselected or outputs are disabled. data is internally latched during a write cycle. output dqg-dqr+inputs data during cui write cycles in x16 mode; outputs data during memory array read cycles in x16 mode; not used for status register and identifier code read mode. data pins float to high-impedance when the chip is deselected, outputs are disabled, or in x8 mode(byte#=v&. data is internally latched during a write cycle. ce# input chip enable: activates the device?s control logic, input buffers, decoders and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. reset/deep power-down: puts the device in deep power-down mode and resets internal automation. rp#-high enables normal operation. when driven low, rp# inhibits write operations rf% input which provides data protection during power transitions. exit from deep power-down sets the device to read array mode. with rp#=v,, block erase or word/byte write can operate to all blocks without wp# state. block erase or word/byte write with vih |